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DIGITAL SIGNAL PROCESSOR
S5L9284D
INTRODUCTION
The S5L9284D is a CMOS integrated circuit designed for the digital audio signal processor. It is a monolithic IC with built-in 16K SRAM and DPLL. It is similar to S5L9283 IC but has advanced error correction ability.
80-QFP-1420C
FEATURES
* * * * * * * * * * * * * EFM data demodulation Built-in frame sync detection, protection and insertion circuit C1: 2 error correction; C2: 4 erasure correction Interpolation Subcode data serial output CLV servo controller Tracking counter MICOM interface Built-in 16K SRAM Digital audio output (TX) Built-in digital PLL and analog PLL Double speed function Single power supply: +5V
ORDERING INFORMATION
Device S5L9284D01-Q0R0 Package 80-QFP-1420C Operating Temperature -20C to +75C
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S5L9284D
DIGITAL SIGNAL PROCESSOR
BLOCK DIAGRAM
KCBS
TDBS
26
SUBCODE SYNC DETECTOR
1S0S
32
33
30 SQDT SUBCODE OUTPUT SUBCODE REGISTER 29 SQCK
EFMI 66 APDO2 80 APDO1 67 VCOI 78 CNTVOL DPFIN DPFOUT DPDO 5 3 DPLL 4 2 FRAME SYNC DETECTOR PROTECTOR INSERTER EFM PHASE DETECTOR 23 BITS SHIFT REGISTER EFM DEMODULATOR
ECC
SMEF 72 16K SRAM SMON 73 SMDP 75 SMSD 76 LOCK 70 XIN XOUT 8 9 X-TAL TIMING GENERATOR CLV SERVO ADDRESS GENERATOR
SUB ATAD TIB-8
MLT 36 MDAT 37 MCK 38 DSPEED 79 /ISTAT 68 TRCNT 69 MODE SELECTOR CPU INTERFACE
TRACK COUNTER
INTERPOLATOR DIGITAL OUTPUT
61
62
63
64
65
22
7
15
12
21
11
20
O P2C
1HCRL
2HCRL
1TDAS
2TDAS
1LES
2LES
3LES
4LES
XTAD
1TSET
0TSET
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DIGITAL SIGNAL PROCESSOR
S5L9284D
PIN CONFIGURATION
DSPEED
APDO2
APDO1
DVDD2
TRCNT
/ISTAT
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
AVDD1 DPDO DPFIN DPFOUT CNTVOL AVSS1 DATX XIN XOUT WDCH1 LRCH1 SADT1 DVSS1 BCK1 C2PO TIM2 /BCK1 /BCK2 BCK2 LRCH2 SADT2 TEST0 WDCH2 EMPH
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TEST1
SMON
VCOO
SMDP
SMSD
SMEF
PBFR
VCOI
LOCK
EFMI
64 63 62 61 60 59 58 57 56
SEL4 SEL3 SEL2 SLE1 /CS /WE C16M C4M /JIT ULKFS FSDW DVSS2 /PBCK FLAG5 FLAG4 FLAG3 FLAG2 FLAG1 DB0 DB1 DB2 DB3 DB4 DB5
KS9284
S5L9284D
55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 S0S1 DB7 MLT RESET MDAT SQDT SBDT MUTE SQOK SQCK SBCK LKFS DVDD1 SQEN MCK DB6
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S5L9284D
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol AVDD1 DPDO DPFIN DPFOUT CNTVOL AVSS1 DATX XIN XOUT WDCH1 LRCH1 SADT1 DVSS1 BCK1 C2PO TIM2 /BCK1 /BCK2 BCK2 LRCH2 SADT2 TEST0 WDCH2 EMPH LKFS S0S1 RESET SQEN SQCK SQDT SQOK I/O - O I O I - O I O O O O - O O O O O O O O I O O O O I I I/O O O Analog supply voltage 1 Charge pump output for master PLL Filter input for master PLL Filter output for master PLL VCO control voltage for master PLL Analog ground 1 Digital audio output X-tal oscillator input (16.9344MHz / 33.8688MHz) X-tal oscillator output Word clock of 48 bits/slot Channel clock of 48 bits/slot Serial audio data output with 48 bits/slot Digital ground 1 Serial audio data bit clock for 48 bits/slot C2 pointer for serial audio data Normal or double speed control output pin Inverted clock of BCK1 Inverted clock of BCK2 Serial audio data bit clock for 64 bits/slot Channel clock for 64 bits/slot Serial audio data output with 64 bits/slot Test input pin ("L": normal, "H": test) Word clock of 64 bit/slot Emphasis/Non-emphasis output ("H": Emphasis) The lock status output of frame sync Output of subcode sync signal (S0 + S1) System reset at Low SQCK control input ("L": internal clock, "H": external clock) Subcode-Q data bit clock Subcode-Q data serial output The CRC check result signal output of subcode-Q Description
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DIGITAL SIGNAL PROCESSOR
S5L9284D
PIN DESCRIPTION (Continued)
Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 Symbol SBCK SBDT DVDD1 MUTE MLT MDAT MCK DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 /PBCK DVSS2 FSDW ULKFS /JIT C4M C16M /WE / CS SEL1 SEL2 I/O I O - I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O - I/O I/O I/O I/O I/O I/O I/O I I Subcode data bit clock Subcode serial data output Digital supply voltage 1 Mute control input ("H": Mute ON) Latch signal input from micom Serial data input from micom Serial data transferring clock input from micom Data port 7 for external SRAM (MSB) Data port 6 for external SRAM Data port 5 for external SRAM Data port 4 for external SRAM Data port 3 for external SRAM Data port 2 for external SRAM Data port 1 for external SRAM Data port 0 for external SRAM (LSB) Monitoring output for C1 error correction (RA0) Monitoring output for C1 error correction (RA1) Monitoring output for C2 error correction (RA2) Monitoring output for C2 error correction (RA3) C2 decoder flag ("H": when the processing C2 code is in impossible correction status /RA4) VCOI/2 clock (4.3218/8.6436 MHz), when locked in with EFMI (RA5) Digital ground 2 Unprotected frame sync (RA6) Frame sync protection status (RA7) RAM overflow and underflow status (RA8) 4.2336 MHz clock output (RA9) 16.9344 MHz clock output (RA10) Write enable output to external SRAM Chip select output to external SRAM X-tal selection terminal ("L":16.9344 MHz, "H": 33.8688 MHz) DPLL selection terminal ("L": DPLL, "H": APLL) Description
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S5L9284D
DIGITAL SIGNAL PROCESSOR
PIN DESCRIPTION (Continued)
Pin No. 63 64 65 66 67 68 69 70 Symbol SEL3 SEL4 TEST1 EFMI APDO1 /ISTAT TRCNT LOCK I/O I I I I O O I O Description CD-ROM selection terminal ("L": CDP, "H": CD-ROM) SRAM selection terminal ("L": internal SRAM, "H": external SRAM) Test terminal ("L": normal, "H": test) EFM data input Charge pump output for analog PLL The internal status output Tracking clock input signal Output signal of LKFS conditions sampled PBFR/16 (If LKFS is High, lock is High. If the LKFS is sampled Low at least 8 times by PBFR/16, lock is Low ) Write frame clock (Lock : 7.35kHz) LPF time constant control of the spindle servo error signal ON/OFF control signal for spindle servo Digital supply voltage 2 Spindle motor driving output (rough control in the speed mode, phase control in the phase mode Spindle motor (Velocity control in the phase mode) VCO output VCO inut (when in locked status by means of PBFR, it is 8.6436MHz) Double speed mode control ("H": normal speed, "L": 2-times speed ) Analog PLL charge pump output for double speed mode
71 72 73 74 75 76 77 78 79 80
PBFR SMEF SMON DVDD2 SMDP SMSD VCOO VCOI DSPEED APDO2
O O O - O O O I I O
NOTES: 1. PBFR: 7.35 kHz Write frame clock produced by data which is being reproduced. 2. /PBCK : Channel bit clock of data which being reproduced. 3. /JIT : Display signal of either RAM overflow or underflow for 4 frame jitter margin.
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DIGITAL SIGNAL PROCESSOR
S5L9284D
ABSOLUTE MAXIMUM RATINGS
Characteristic Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature Symbol VDD VI VO TOPR TSTG Value -0.3 -- + 7.0 -0.3 -- + 7.0 -0.3 -- + 7.0 -20 -- + 75 -40 -- + 125 Unit V V V C C
ELECTRICAL CHARACTERISTICS
DC Characteristics (VDD = 5 V, VSS = 0 V, Ta = 25C, unless otherwise specified) Characteristic High Input Voltage1 Low Input Voltage1 High Input Voltage2 Low Input Voltage2 High Outut Voltage1 Low Output Voltage1 High Outut Voltage2 Low Output Voltage2 High Outut Voltage3 Low Output Voltage3 Input Leak Current1 Input Leak Current2 Tri-State Output Leak Current Symbol VIH (1) VIL(1) VIH (2) VIL (2) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) ILKG1 ILKG2 IO (LKG) Test Conditions (Note 1) (Note 1) (Note 2) (Note 2) IOH = -1mA( Note 3) IOL = 1mA (Note 3) IOH = -1mA (Note 4) IOL = 1mA (Note 4) IOH = -1mA (Note 5) IOL = 1mA (Note 5) VI = 0 to VDD (Note 6) VO = 0 to V DD (Note 7) V I = 0 to VDD (Note 8) Min 0.7VDD - 0.8VDD - VDD - 0.5 0 VDD - 0.5 0 VDD - 0.5 0 -5 -10 -5 Typ - - - - - - - - - - - - - Max - 0.3VDD - 0.2VDD VDD 0.4 VDD 0.4 VDD 0.4 +5 +10 +5 Unit V V V V V V V V V V mA mA mA
NOTES: 1. Input Voltage1: All input pins 2. Input Voltage2: All BIDIR pins 3. Output Voltage1: All output pins 4. Output Voltage2: All BIDIR pins 5. Output Voltage 3: All Tri - state output pins 6. Input Leak Current 1: All input pins except for XIN, VCOI 7. Input Leak Current 2: XIN, VCOI 8. Output Leak Current : SMEF, SMDP, SMSD, APDO1, APDO2, DPDO
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S5L9284D
DIGITAL SIGNAL PROCESSOR
AC CHARACTERISTICS A. XIN, VCOI (When the pulse is input to) (VDD = 5 V, VSS = 0 V, Ta = 25C, unless otherwise specified) Characteristic High Level Pulse Width Low Level Pulse Width Pulse Frequency Input High Level Input Low Level Rising & Falling Time Symbol tw H tw L tCK VIH VIL tR, tF Min 13 13 26 VDD - 1.0 - - Typ - - - - - - Max - - - - 0.8 8 Unit ns ns ns V V ns
tCK tWH tWL
VIH VIH X 0.9
VDD/2
VIH X 0.1 VIL tR tL
Figure 1.
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DIGITAL SIGNAL PROCESSOR
S5L9284D
B. MCK, MDAT, MLT, TRCNT (VDD = 5 V, VSS = 0 V, Ta = 25C, unless otherwise specified) Characteristic Clock Frequency Clock Pulse Width Setup Time Hold Time Delay Time Latch Pulse Width TRCNT, SQCK Frequency TRCNT, SQCK Pulse Width Symbol fCK 1 tW tSU tH tD tWCK1 fCK 2 tWCK2 Min 300 300 300 300 300 - 300 Typ - - - - - - - - Max 1 - - - - - 1 - Unit MHz ns ns ns ns ns MHz ns
tWCK1
1/fCK1 tWCK1
MCK
MDAT MLT
tSU tH
tD
tW
TRCNT SQCK
tWCK2
tWCK2
1/fCK2
SQDT
tSU tH
Figure 2.
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S5L9284D
DIGITAL SIGNAL PROCESSOR
FUNCTION DESCRIPTION MICOM INTERFACE
The data input from MICOM is input to MDAT and transported by MCK. The input signal is loaded to the control register by means of MLT. The timing chart is as follows.
MDAT MCK MLT Register CNTL-Z ~ CNTL-D
D0
D1
D2
D3
D4
D5
D6
D7(MSB)
Valid
Figure 3. MICOM Data Input Timing Chart
Control Register CNTL-Z CNTL-S CNTL-L CNTL-U CNTL-W CNTL-C CNTL-D
Comment
Address D7 -- D4 1001 1010 1011 1100 1101 1110 1111
Data D3 ZCMT FSEM TRC3 TRC7 COM - D2 HIPD FSEL TRC2 TRC6 WB - D1 NCLV WSEL TRC1 TRC5 WP D0 CRCQ ATTM TRC0 TRC4 GAIN
/ISTAT Terminal HI-Z HI-Z /Complete /Count HI-Z /(Pw 64)
Data Control Frame Sync Protection Attenuation Control Tracking Counter Lower 4 Bits Tracking Counter Upper 4 Bits CLV Control CLV Mode Double Speed
CLV Mode DS1 DS2
HI-Z
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DIGITAL SIGNAL PROCESSOR
S5L9284D
CNTL-Z Register It is a register to control the zero cross mute of audio data, the phase terminal control, the phase servo and having CRCF data in SQDT or not. DATA ZCMT HIPD NCLV CRCQ D3 D2 D1 D0 DATA = 0 Zero cross mute is OFF It operates phase normally Phase servo is acted by frame sync SQDT output except for SQOK DATA = 1 Zero cross mute is ON The phase becomes "L" to "Hi-Z" Phase servo is controlled by base counter SQDT = CRCF when S0S1 = "H"
CNTL-S Register It is a register to control frame sync protection and attenuation. FSEM 0 0 1 1 FSEL 0 1 0 1 FRAME 2 4 8 13 WSEL 0 1 CLOCK 3 7 ATTM 0 0 1 1 MUTE 0 1 0 1 dB 0 - - 12 - 12
CNTL-L, U Register After the number of tracks that must be counted is input from micom , the data is loaded to the tracking counter by the CNTL-L, U register.
CNTL-W Register It is a register to control CLV-servo. DATA COM WB WP GAIN D3 D2 D1 D0 DATA = 0 DATA = 1 Comment Phase comparison frequency control during Phase - mode Bottom hold period control during speed or HSpeed-mode Peak hold period control during Speed-mode SMDP gain control during Speed or HSpeed-Mode
XTFR/4 and PBFR/4 XTFR/32 XTFR/4 -12dB XTFR/16 XTFR/2 0dB
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S5L9284D
DIGITAL SIGNAL PROCESSOR
CNTL-C Register Mode Forward Reverse Speed Hspeed Phase XPHSP VPHSP Stop D7-D4 1110 D3-D0 1000 1010 1110 1100 1111 0110 0101 0000 H L Speed-mode Hspeed-mode Phase-mode Speed, phase-mode Speed, Phase-mode L SMDP SMSD Hi-Z Hi-Z Hi-Z Hi-Z Phase-mode Hi-Z, Phse-mode Hi-Z, Phase-mode Hi-Z SMEF L L L L Hi-Z L, Hi-Z L, Hi-Z L SMON H H H H H H H L
CNTL-D Register It is a register to control normal speed mode and double speed mode. Mode Normal Double D7-D4 1111 D3-D0 XX00 XX11 Comment Normal Speed Double Speed
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DIGITAL SIGNAL PROCESSOR
S5L9284D
TRACKING COUNTER
This block is used to improve track-jump characteristics. The number of tracks, which must be jumped, is input from micom, and the operating of the count is performed by the TRCNT pulse at the positive edge of MLT. If the number of tracks is loaded into the register and the CNTL-L is selected, the /COMPLETE signal is output to the /ISTAT terminal, and if the CNTL-U is selected, the /COUNT signal is output. The following is the timing chart of the tracking counter block.
MLT CNTL-L,U
N Tracking Count Data Loading
TRCNT /ISTAT =(/COUNT) /ISTAT =(/COMPLETE)
N N N N N N N
Figure 4. Tracking Counter Timing Chart
MDAT
MLT CNTL State /ISTAT
CNTL-L /COMPLETE CNTL-U /COUNT CNTL-C /(PW > 64) Other Mode Hi-Z
Figure 5. /ISTAT Output Signal According to CNTRL Register
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S5L9284D
DIGITAL SIGNAL PROCESSOR
EFM DEMODULATION BLOCK
This block consists of an EFM demodulator which demodulates EFM data obtained from a disc, an EFM phasedetector and a controller, etc. EFM PHASE DETECTOR As the EFM signal input from a disc includes the components of 2.1609 MHz, the EFM phase detector uses the bit clock (/PBCK) of 4.3218 MHz, to detect the phase of this signal. This PBCK detects the phase at the edge of the EFM signal and the result is output to the APDO1 or APDO2 terminals. A. At Normal Operating
VCOI: PBCK: EFMI: EFMD: APDO:
Hi-Z
1
Hi-Z
2
Hi-Z
3
Hi-Z
In case of (1) : When the EFM signal is slower than VCO In case of (2) : When the EFM signal is locked with VCO In case of (3) : When the EFM signal is faster than VCO Figure 6. Timing Chart of the EFM Phase Detector B. At Abnormal Operating If the HIPD of CNTL-Z is "H" and "L" of the LKFS is shorter than 3.5T (a period PBFR is T), the Hi-Z is output to the APDO terminal as many as "L" , and if it is over 3.5T, the Hi-Z is output as many as 3.5T. EFM DEMODULATOR The 14-bit data is channeled through the circuit, and is de modulated to 8-bit data. Demodulated data has two kinds of signals, One is subcode data and the other is audio data. They are respectively input into the subcode block written in the internal 16K SRAM to perform error correction.
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DIGITAL SIGNAL PROCESSOR
S5L9284D
FRAME SYNC DETECTOR, PROTECTOR AND INSERTER A. Frame Sync Detector The data consists of frame units, which include frame sync, subcode data, PCM data, redundancy data, etc. The frame sync is detected in order to maintain the sync. B. Frame Sync Protector/Inserter Occasionally, the frame sync is omitted or detected in a place where it doesn't exist by the effect of error or jitter on a disc. In these cases, we need to protect or insert the signal. A window is made to protect the frame sync by using the WSEL. If the frame sync is input to the window, it is true data, and if isn't input, it is ignored. The width of the window is determined by WSEL of the CNTL-S register. If the frame sync is not detected in the frame sync protection window, one sync which is made by the internal counter block, is inserted in sequence. When the appointed number of frames is achieved by FSEM, FSEL of the CNTL-S register, the ULKFS becomes "L" and the frame sync protection window is ignored. The frame sync is received absolutely at that time. When the frame sync is received, the ULKFS signal becomes "H" and the frame sync window is received. LKFS 1 0 ULKFS 1 1 Comment Corresponding with playback frame sync and generated frame sync 1. Out of correspondence with playback frame sync generated frame sync, but PBFR sync is detected in the window selected by WSEL. 2. Out of correspondence with PBFR sync and XTFR sync, and sync is inserted because it isn't detected in the window selected by WSEL. 1. After inserting as many frames as decided by FSEM and FSEL of the CNTL-S register, and the window is ignored. 2. In case that the PBFR sync is not detected continually after (1).
0
0
SUBCODE BLOCK
The subcode sync signal (that is S0, S1) is detected in the subcode sync block. When S0 is detected, S1 is detected after one frame. At that time, the S0 + S1 signal is output to the S0S1 terminal, and the S0S1 signal is output to the SBDT terminal when the S0S1 signal is "H". The subcode data among the data input to the EFM terminal, is demodulated to 8-bit subcode data (P, Q, R, S, T, U, V, W). It is synchronized with the PBFR signal and is output to SBDT by the SBCK clock. Among the eight subcode data, only Q data is selected and loaded to the eighty shift register by the PBFR signal. The result of the CRC (Cycle Redundancy Check) of loading data, is synchronized with the S0S1 positive edge and output to the SQOK terminal. If the result is error, "L" is output to the SQOK terminal, and if it is true, "H" is output instead. If the CRCD of CNTL-Z mode is "H", the result of CRC checking is output to the SQDT terminal from the S0S1 section "H" to the period of the SQCK negative edge. The following is the timing chart of the subcode block
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S5L9284D
DIGITAL SIGNAL PROCESSOR
At SQEN = "L": SBDT, SQDT, S0S1, SQOK, VCOI Timing Chart.
T VCOI : PBFR : S0S1 : SQOK : SQCK : SDAT : 8T SQDT :
Figure 7. Subcode-Q Timing Chart 1 At SQEN = "L": SQOK, SQDT, S0S1 Timing Chart
2T
SQCK : S0S1 : SQOK : SQDT :
Q96 Q97 SQOK Q1 Q2 Q3 Q4 Q5 Q6 Q94 Q95 Q96 Q97 SQOK Q1 Q2
Figure 8. Subcode-Q Timing Chart 2 At SQEN = "H": SQOK, SQDT, S0S1, Timing Chart
S0S1 : SQOK : SQCK : SQDT : CRCQ=0 SQDT : CRCQ=1
0 Q4 Q3 Q2 Q1 Q8 Q7 Q6 Q5 Q12 Q80 Q79 Q78 Q77 0 Q4 Q3
SQOK(n)
Q4
Q3
Q2
Q1
Q8
Q7
Q6
Q5
Q12
Q80
Q79
Q78
Q77 SQOK(n+1) Q4
Q3
Figure 9. Subcode-Q Timing Chart 3
16
DIGITAL SIGNAL PROCESSOR
S5L9284D
(Comment) : If the SQOK of the subcode Q data is "H", the subcode data is output to SQDT according to the SQCK signal. If the SQOK is "L", it is output to SQDT with "L". VCOI, SBDT, SBCK Timing Chart.
T
VCOI : PBFR :
1
1
2
2
3
4
5
6
7
8
SBCK : SDAT :
3
Q
R
S
T
U
V
W
4
Figure 10. Timing Chart of Subcode Data Output (1) : After PBFR becomes negative edge, SBCK becomes "L" for about 10 msec. (2) : If S0S1 is "L", subcode P is output, and if "H", S0S1 is output. (3) : If a period of VCOI is "T", the width of (3) is 4T. (4) : If the pulse input to the SBCK terminal is over seven, subcode data (P, Q, R, S, T, U, V, W) is repeated.
ECC (ERROR CORRECTION CODE) BLOCK
The function of the ECC block is to recover damaged data to some extent when data on a disc is damaged. By using the CIRC (Cross Interleaved Reed-Solomon Code), 2-Error correction is performed for C1 (32, 28) and 4erasure correction is performed for C2 (28, 24). ECC is performed by the unit of one symbol of eight bits. In correcting C1, a C1 pointer is generated, and in correcting C2, the C2 pointer is generated. C1, C2 pointers send error information to the data which ECC is given. After correcting C2, against uncorrectable data, error data is sent to display by outputting a C2 FLAG. This information data is input to the interpolator block in order to handle error data. The monitoring flow for error correction is available through FLAG1 ~ FLAG5 terminals. The monitoring flow for error correction MODE C1 0,1 error C1 2 error C1 irretrievable error C1 0,1,2 error C2 0,1,2,3,4 error C2 irretrievable error 1 C2 irretrievable error 2 FLAG5 0 0 0 0 1 1 1 FLAG4 1 1 1 1 1 1 1 FLAG3 1 1 1 1 1 1 1 FLAG2 1 1 1 1 0 1 1 FLAG1 0 1 1 1 1 0 1 REMARK - - - Attenuation - - C1 point copy 1
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S5L9284D
DIGITAL SIGNAL PROCESSOR
INTERPOLATION / MUTE BLOCK
Interpolator When a burst error occurs on a disc, sometimes the data can't be corrected even if an ECC process is performed. The interpolator block revises data by using a C2 pointer output through the ECC block.The data input to a data bus is input to the left and right channel, respectively, in the order of the lower 8-bit and the upper 8-bit. A pre-hold method is taken when a C2 pointer is "H" continuously. In case of a single error, an everage interpolation method is carried out with the range of the data before and after an error happens. When LRCH signal during one LRCH cycle is "L", R-CH data is output, L-CH data is output when the check is "H".
A B C G D E F H I J
B = A+C ; average interpolation 2 F= E = D : provious datahold
C2 pinter
G = F+H ; average interpolation 2 Figure 11. Interpolation.
Mute and Attenuation By using a mute terminal and the ATTM signal of the CNTL-S register, audio data is muted or attenuated.There are two kinds of mute: zero-cross muting and muting A. Zero-Cross Muting The audio data is muted, after ZCMT of CNTL-Z register goes to "H". In that case the mute is "H" and the upper 6bit of audio data became all "L" or "H". B. Muting The audio data is muted when ZCMT of the CNTL-Z register is "L" and the mute terminal is "H". C. Attenuation The signal attenuation occurs by the means of the ATTM of the CNTL-Z register, and the mute signal as shown the following,. Attm 0 0 1 1 Mute 0 1 0 1 Degree of Attenuation 0 dB - dB -12 dB -12 dB
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DIGITAL SIGNAL PROCESSOR
S5L9284D
DIGITAL AUDIO OUT BLOCK
The 2 channel, 16-bit data is connected and output serially to other digital systems by the digital audio interface format.
191R
0L
0R
1L
1R
****
190L
190R
191L
191R
0L
0R
T
192T = 1 BLOCK
Figure 12. 0L: L-CH format includs block sync preamble. 1L ~ 191L: L-CH format includs L-CH sync preamble. 0R ~ 191R: R-CH format includs R-CH sync preamble.
1 LRCH 32 bit
L-CH
32 bit
R-CH
PREAMBLE
Modulated `0' 8 bits
Modulated 16 bits audio data
V
U
C
P
Control Signal Figure 13. Digital Audio Out Format
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S5L9284D
DIGITAL SIGNAL PROCESSOR
A. Preamble It is used to discriminate between the block sync of data and L/R-channel of data.
L-CH SYNC (Except for block sync) R-CH SYNC
Block SYNC (L-CH) 4 bit Figure 14. Preamble Signal B. Control signal (1) Validity bit: It indicate that the error of 16-bit audio data exists, or doesn't ("H" : error, "L": valid data) (2) User definable bit: Subcode data input.
S0S1 PBFR SBCK SBDT
SYNC PATTERN P Q R S T U V W P
Figure 15. Timing Chart of Digital Audio Out (3) Channel status bit: The upper 4-bit of subcodes Q indicate the number of channels, pre-emphasis copy and CDP category, etc.
S0S1 SQOT
ID0 ID1 COPY EMPH
H
PBFR
Figure 16. Timing Chart of Channel Status Data Output (4) Parity bit: Making even parity
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DIGITAL SIGNAL PROCESSOR
S5L9284D
CLV SERVO BLOCK
The CNTL-C register is selected to control the CLV (Constant Linear Velocity) servo by the data input from micom. In the CNTL-C register, the CLV servo action mode is appointed by the data input from micom to control the spindle motor. In case of a double-speed setting, the CNTL-C register has to be selected after the CNTL-D register sets, so that it is able to detect / (Pw 64) signal from the /ISTAT terminal.
Forward Mode The status of the related output terminals are as follows. SMDP H Reverse Mode The status of the related output terminals are as follows. SMDP L Speed-Mode The speed-mode is the mode for the rough control of a spindle motor when a track is jumping or when an EFM phase is unlocked. If a period of VCO is "T", the pulse width of frame sync is "22T". In case that the signal detected from an EFM signal exceeds "22T" by noise on the disc.... etc., it must be removed. If not, the right frame sync can't be detected. In this case, the pulse width of the EFM signal is detected by peak and bottom hold clock. The peak hold clock is XTFR/2 or XTR/4, and the bottom hold clock is XTFR/16 or XTFR/32. The detected value is used for the synchronized frame signal. If a synchronized frame signal is less than 21T, the SMDP terminal outputs "L". When it is equal to 22T, it outputs "HiZ", and when it is more than 23T, it outputs "H". If the gain signal of the CNTLW register is "L", the output of SMDP terminal is reduced up to - 12 dB. If it is "H", there is no reduction. Hi-Speed-Mode The rough servo mode, which moves 20,000 tracks in high speed, acts between the inner and outer peripheries of the CD. The track's mirror domain ( where there are no pits ) is duplicated with 20 kHz signals to the EFM. In this case, the servo action is unstable, because, the peak value of the mirror signal is longer than the original frame signal, which is detected. In Hspeed mode, by using the 8.4672/256 MHz signal against peak hold, and the XTFR/ 16 or XTFR/32 signal against bottom hold, the mirror is removed , and the Hspeed action becomes stable . The output conditions in Hspeed mode are: SMSD is "Hi-Z", "SMEF" is "L", and SMON is "H". SMDP - Phase-Mode The phase-mode is the mode to control the EFM phase. Phase difference between PBFR/4 and XTFR/4 is detected when NCLV of CNTL-Z is "L" and the difference is output to the SMDP terminal. If a cycle of VCO/2 signal is put as "T" and it is put as "/WP" during an "H" period of PBFR, it outputs "H" to the SMSD terminal from the falling edge of PBFR to the (/WP-278T) X 32, and then, outputs "L" to the falling edge of the next. SMSD Hi-Z SMEF L SMON H SMSD Hi-Z SMEF L SMON H SMSD Hi-Z SMEF L SMON H
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S5L9284D
DIGITAL SIGNAL PROCESSOR
XPHSP-Mode The XPHSP mode is the mode used in normal operation. It samples a LKFS signal made in the frame sync block at a cycle of PBFR/16. If the sampling is "H", the phase mode is performed, and if "L" is sampled 8 times consecutively, the speed mode is performed automatically. The selection of peak hold period of speed mode, and bottom hold period and gain of speed / Hspeed mode is determined by the CNTL-W register. VPHSP-Mode The VPHSP-mode is the mode used for rough servo control. It uses VCO instead of X-tal in the EFM pattern test. When the range of VCO center changes, VCO is easily locked because the rotation of a spindle motor changes in the same direction. STOP Stop is the mode used to stop the spindle motor. SMDP L SMSD Hi-Z SMEF L SMON L
XTFR/4 : (XTFR/8) PBFR/4 : ( PBFR/8) SMPD :
Hi-Z Hi-Z Hi-Z
Figure 17. Timing Chart SMDP Output
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DIGITAL SIGNAL PROCESSOR
S5L9284D
287T PBFR : 288T SMSD :
(a) Timing Chart of SMSD Output When PBFR is "287T"
294T PBFR : 512T SMSD :
(b) Timing Chart of SMSD Output When PBFR is "294T" Figure 18. Timing Chart of SMSD Output at Phase Mode.
TB PHC: BHC:
1
TP
22T
2
21T >
> 23noise
3
EFM Width EFM Width
( > 22T):
( > 23T):
PH F/F
( > 22T):
1 PH F/F
( > 23T):
1
0
1
0
BH F/F BH F/F
(>22T) :
1
1
0
1
1
0
(> 23T) :
0
1
1
0
Latch
( 22T ) :
0
1
0
Latch SMPD:
( 23T ) :
1 Z : 225T ( output for 1 )
1 L : > 21T ( output for 2 )
0 H : (output for 3 )
Figure 19. Timing Chart of SMPD Output When the Gain is "H" in the Speed Mode
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S5L9284D
DIGITAL SIGNAL PROCESSOR
DIGITAL PLL BLOCK
This device contains analog PLL and digital PLL together, in order to obtain the stable channel clock for demodulating the EFM signal. The block diagram of digital PLL is as follows.
X - Tal
Voltage Controlled
Low Pass Filter
Voltage Controlled Oscillator
I/N Divider
Digital PLL
/PBCK
Figure 20. The Application Diagram of Digital PLL
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